SH7136 datasheet(175/1160 Pages) RENESAS

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Section 7 User Break Controller (UBC)

Rev. 2.00 Sep. 10, 2008 Page 149 of 1130

REJ09B0402-0200

7.4.7

Usage Examples

Break Condition Specified for L Bus Instruction Fetch Cycle:

(Example 1-1)

• Register specifications

BARA = H'00000404, BAMRA = H'00000000, BBRA = H'0054, BDRA = H'00000000,

BDMRA = H'00000000, BARB = H'00008010, BAMRB = H'00000006, BBRB = H'0054,

BDRB = H'00000000, BDMRB = H'00000000, BRCR = H'00000400

Specified conditions: Channel A/channel B independent mode

Address:

H'00000404, Address mask: H'00000000

Data:

H'00000000, Data mask: H'00000000

Bus cycle: L bus/instruction fetch (after instruction execution)/read (operand size is not

included in the condition)

Address:

H'00008010, Address mask: H'00000006

Data:

H'00000000, Data mask: H'00000000

Bus cycle: L bus/instruction fetch (before instruction execution)/read (operand size is not

included in the condition)

A user break occurs after an instruction of address H'00000404 is executed or before

instructions of addresses H'00008010 to H'00008016 are executed.

(Example 1-2)

• Register specifications

BARA = H'00037226, BAMRA = H'00000000, BBRA = H'0056, BDRA = H'00000000,

BDMRA = H'00000000, BARB = H'0003722E, BAMRB = H'00000000, BBRB = H'0056,

BDRB = H'00000000, BDMRB = H'00000000, BRCR = H'00000008

Specified conditions: Channel A/channel B sequential mode

Address:

H'00037226, Address mask: H'00000000

Data:

H'00000000, Data mask: H'00000000

Bus cycle: L bus/instruction fetch (before instruction execution)/read/word

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