HD64F36034 datasheet(346/592 Pages) RENESAS

346 / 592 page

Section 15 Controller Area Network for Tiny (TinyCAN)

Rev. 4.00 Mar. 15, 2006 Page 314 of 556

REJ09B0026-0400

• TCIRR1

Bit

Bit Name

Initial

Value

R/W

Description

7 to 5

—

All 0

—

Reserved

These bits are always read as 0.

WUPI

R/(W)* Wakeup Interrupt Flag

Status flag indicating detection of a dominant bit on the

CAN bus while the LSI is in standby mode. This flag can

be set to 1 only in standby mode.

[Setting condition]

When the falling edge of HRXD is detected in standby

mode

[Clearing condition]

When 1 is written to this bit

3, 2

—

All 0

—

Reserved

These bits are always read as 0.

OVRI

Unread Message Interrupt Flag

Status flag indicating that a new message has been

received regardless of existence of an unread message.

The NMC bit in MCn0 (n = 0 to 3) will determine how to

handle the newly received message: NMC = 1 selects

overwrite and NMC = 0 selects overrun (ignore).

[Setting condition]

When a new message is received with the MBIMR

corresponding to the receive message cleared to 0 and

the corresponding bit in RXPR or RFPR set to 1

[Clearing condition]

When all bits in UMSR are cleared to 0

EMPI

Mailbox Empty Interrupt Flag

Status flag indicating that the next transmit message can

be written to the Mailbox.

[Setting condition]

When TXPR is cleared to 0 by completion of transmission

or completion of transmission cancellation

[Clearing condition]

When TXACK and ABACK is cleared to 0

Note:

Only 1 can be written to clear the flag.

HD64F36034 Datasheet(PDF) 346 Page - Renesas Technology Corp

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