HD64F36034 datasheet(220/592 Pages) RENESAS

220 / 592 page

Section 12 Timer Z

Rev. 4.00 Mar. 15, 2006 Page 188 of 556

REJ09B0026-0400

Free-Running Count Operation and Periodic Count Operation: Immediately after a reset, the

TCNT counters for channels 0 and 1 are all designated as free-running counters. When the

relevant bit in TSTR is set to 1, the corresponding TCNT counter starts an increment operation as

a free-running counter. When TCNT overflows, the OVF flag in TSR is set to 1. If the value of the

OVIE bit in the corresponding TIER is 1 at this point, timer Z requests an interrupt. After

overflow, TCNT starts an increment operation again from H'0000.

Figure 12.8 illustrates free-running counter operation.

H'FFFF

TCNT value

Time

H'0000

STR0,

STR1

OVF

Figure 12.8 Free-Running Counter Operation

When compare match is selected as the TCNT clearing source, the TCNT counter for the relevant

channel performs periodic count operation. The GR registers for setting the period are designated

as output compare registers, and counter clearing by compare match is selected by means of bits

CCLR1 and CCLR0 in TCR. After the settings have been made, TCNT starts an increment

operation as a periodic counter when the corresponding bit in TSTR is set to 1. When the count

value matches the value in GR, the IMFA, IMFB, IMFC, or IMFD flag in TSR is set to 1 and

TCNT is cleared to H'0000.

If the value of the corresponding IMIEA, IMIEB, IMIEC, or IMIED bit in TIER is 1 at this point,

the timer Z requests an interrupt. After a compare match, TCNT starts an increment operation

again from H'0000.

HD64F36034 Datasheet(PDF) 220 Page - Renesas Technology Corp