HD64F36034 datasheet(280/592 Pages) RENESAS

280 / 592 page

Section 13 Watchdog Timer

Rev. 4.00 Mar. 15, 2006 Page 248 of 556

REJ09B0026-0400

13.2.2

Timer Counter WD (TCWD)

TCWD is an 8-bit readable/writable up-counter. When TCWD overflows from H'FF to H'00, the

internal reset signal is generated and the WRST bit in TCSRWD is set to 1. TCWD is initialized to

H'00.

13.2.3

Timer Mode Register WD (TMWD)

TMWD selects the input clock.

Bit

Bit Name

Initial

Value

R/W

Description

CKS7

R/W

Clock Select 7

Selects the subtimer internal oscillator.

CKS7 CKS3

: SBT internal oscillator

: WDT internal oscillator

6 to 4



All 1



Reserved

These bits are always read as 1.

CKS3

CKS2

CKS1

CKS0

R/W

Clock Select 3 to 0

Select the clock to be input to TCWD.

1000: Internal clock: counts on

φ/64

1001: Internal clock: counts on

φ/128

1010: Internal clock: counts on

φ/256

1011: Internal clock: counts on

φ/512

1100: Internal clock: counts on

φ/1024

1101: Internal clock: counts on

φ/2048

1110: Internal clock: counts on

φ/4096

1111: Internal clock: counts on

φ/8192

0XXX: WDT internal oscillator

For the internal oscillator overflow periods, see section

22, Electrical Characteristics.

[Legend]

X: Don't care.

HD64F36034 Datasheet(PDF) 280 Page - Renesas Technology Corp

HD64F36034 Datasheet(HTML) 280 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL