SH7124 datasheet(161/774 Pages) RENESAS

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Section 7 User Break Controller (UBC)

Rev. 4.00 Jul. 25, 2008 Page 141 of 750

REJ09B0243-0400

Address:

H'0003722E, Address mask: H'00000000

Data:

H'00000000, Data mask: H'00000000

Bus cycle: L bus/instruction fetch (before instruction execution)/read/word

Since instruction fetch is not a write cycle on channel A, a sequential condition does not

match. Therefore, no user break occurs.

(Example 1-5)

• Register specifications

BARA = H'00000500, BAMRA = H'00000000, BBRA = H'0057, BDRA = H'00000000,

BDMRA = H'00000000, BARB = H'00001000, BAMRB = H'00000000, BBRB = H'0057,

BDRB = H'00000000, BDMRB = H'00000000, BRCR = H'00000001, BETR = H'0005

Specified conditions: Channel A/channel B independent mode

Address:

H'00000500, Address mask: H'00000000

Data:

H'00000000, Data mask: H'00000000

Bus cycle: L bus/instruction fetch (before instruction execution)/read/longword

The number of execution-times break enable (5 times)

Address:

H'00001000, Address mask: H'00000000

Data:

H'00000000, Data mask: H'00000000

Bus cycle: L bus/instruction fetch (before instruction execution)/read/longword

On channel A, a user break occurs after the instruction of address H'00000500 is executed four

times and before the fifth time.

On channel B, a user break occurs before an instruction of address H'00001000 is executed.

(Example 1-6)

• Register specifications

BARA = H'00008404, BAMRA = H'00000FFF, BBRA = H'0054, BDRA = H'00000000,

BDMRA = H'00000000, BARB = H'00008010, BAMRB = H'00000006, BBRB = H'0054,

BDRB = H'00000000, BDMRB = H'00000000, BRCR = H'00000400

Specified conditions: Channel A/channel B independent mode

Address:

H'00008404, Address mask: H'00000FFF

Data:

H'00000000, Data mask: H'00000000

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