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SH7032 Datasheet(PDF) 55 Page - Renesas Technology Corp |
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SH7032 Datasheet(HTML) 55 Page - Renesas Technology Corp |
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55 / 687 page ![]() Section 2 CPU Rev. 7.00 Jan 31, 2006 page 29 of 658 REJ09B0272-0700 Instruction Format Source Operand Destination Operand Example nm format mmmm : Register direct nnnn : Register direct ADD Rm,Rn nnnn xxxx xxxx 15 0 mmmm mmmm : Register direct nnnn : Register indirect MOV.L Rm,@Rn mmmm : Register indirect with post- increment (multiply- and-accumulate) nnnn : Register indirect with post- increment (multiply- and-accumulate)* MACH, MACL MAC.W @Rm+,@Rn+ mmmm : Register indirect with post-increment nnnn : Register direct MOV.L @Rm+,Rn mmmm : Register direct nnnn : Register indirect with pre-decrement MOV.L Rm,@-Rn mmmm : Register direct nnnn : Indexed register indirect MOV.L Rm,@(R0,Rn) md format xxxx dddd 15 0 mmmm xxxx mmmmdddd : Register indirect with displacement R0 (Register direct) MOV.B @(disp,Rn),R0 nd4 format xxxx xxxx dddd 15 0 nnnn R0 (Register direct) nnnndddd: Register indirect with displacement MOV.B R0,@(disp,Rn) nmd format nnnn xxxx dddd 15 0 mmmm mmmm : Register direct nnnndddd : Register indirect with displacement MOV.L Rm,@(disp,Rn) mmmmdddd : Register indirect with displacement nnnn : Register direct MOV.L @(disp,Rm),Rn |
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