SH7032 datasheet(10/687 Pages) RENESAS

10 / 687 page

Rev. 7. 00 Jan 31, 2006 page x of xxvi

Item

Page

Revision (See Manual for Details)

2.4.1 Instruction

Set by Classification

Table 2.13

Arithmetic

Instructions

Table amended

Instruction

Instruction Code

Operation

Execution

Cycles

T Bit

MAC.W

@Rm+,@Rn+

0100nnnnmmmm1111

Signed operation of

(Rn)

× (Rm) + MAC →

MAC

× 16 + 42 → 42-bit

3/(2)

—

MULS

Rm,Rn

0010nnnnmmmm1111

Signed operation of

× Rm → MAC

× 16 → 32-bit

1–3

—

MULU

Rm,Rn

0010nnnnmmmm1110

Unsigned operation of

× Rm → MAC

× 16 → 32-bit

1–3

—

2.4.2 Operation

Code Map

Table 2.18

Operation Code

Map

42, 43

Table amended

Instruction Code

Fx: 0000

Fx: 0001

Fx: 0010

Fx: 0011–1111

MSB

LSB MD: 00

MD: 01

MD: 10

MD: 11

0000

1001

NOP

DIV0U

0000

1001

MOVT Rn

0110

10MD SWAP.B

Rm,Rn

SWAP.W

Rm,Rn

NEGC

Rm,Rn

NEG

Rm,Rn

8.5.3 Wait State

Control

151

Description amended

Regardless of the state of the

WAIT signal, when the RW1 bit, the

number of wait states selected by CBR refresh wait state insertion

bits 1 and 0 (RLW1, RLW0) in the refresh control register (RCR)

are inserted into the CAS-before-RAS refresh cycle.

10.4.5 Reset-

Synchronized PWM

Mode

Figure 10.31

Procedure for

Selecting Reset-

Synchronized PWM

Mode

273

Description of PFC setting added

10.4.6

Complementary

PWM Mode

Figure 10.33

Procedure for

Selecting

Complementary

PWM Mode

276

Description of PFC setting added

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