SH7108 datasheet(109/560 Pages) RENESAS

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Section 6 Interrupt Controller (INTC)

Rev.1.00 Sep. 18, 2008 Page 75 of 522

REJ09B0069-0100

6.2

Input/Output Pins

Table 6.1 shows the INTC pin configuration.

Table 6.1

Pin Configuration

Name

Abbreviation

I/O

Function

Non-maskable interrupt input pin

NMI

Input

Input of non-maskable interrupt

request signal

Interrupt request input pins

IRQ0 to IRQ3

Input

Input of maskable interrupt request

signals

Interrupt request output pin

IRQOUT

Output

Output of notification signal when an

interrupt has occurred

6.3

The interrupt controller has the following registers. For details on register addresses and register

states during each processing, refer to section 19, List of Registers.

• Interrupt control register 1 (ICR1)

• Interrupt control register 2 (ICR2)

• IRQ status register (ISR)

• Interrupt priority register A (IPRA)

• Interrupt priority register D (IPRD)

• Interrupt priority register E (IPRE)

• Interrupt priority register F (IPRF)

• Interrupt priority register G (IPRG)

• Interrupt priority register H (IPRH)

• Interrupt priority register I (IPRI)

• Interrupt priority register J (IPRJ)

• Interrupt priority register K (IPRK)

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