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HD6433635SW Datasheet(PDF) 187 Page - Renesas Technology Corp |
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HD6433635SW Datasheet(HTML) 187 Page - Renesas Technology Corp |
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187 / 418 page ![]() 173 Bits 2 to 0—Clock Select L (CKSL2 to CKSL0): Bits 2 to 0 select the input to TCFL from four internal clock signals or external event input. Bit 2: CKSL2 Bit 1: CKSL1 Bit 0: CKSL0 Description 0 ** External event (TMIF). Rising or falling edge is counted (see note). (initial value) 1 0 0 Internal clock: ø/32 1 Internal clock: ø/16 1 0 Internal clock: ø/4 1 Internal clock: ø/2 *: Don’t care Note: The edge of the external event signal is selected by bit IEG3 in the IRQ edge select register (IEGR). See 3.3.2, Interrupt Control Registers, for details on the IRQ edge select register. Note that switching the TMIF pin function by changing bit IRQ3 in port mode register 1 (PMR1) from 0 to 1 or from 1 to 0 while the TMIF pin is at the low level may cause the timer F counter to be incremented. Timer Control/Status Register F (TCSRF) Bit 76543210 OVFH CMFH OVIEH CCLRH OVFL CMFL OVIEL CCLRL Initial value 00000000 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W TCSRF is an 8-bit read/write register. It is used for counter clear selection, overflow and compare match indication, and enabling of interrupts caused by timer overflow. Upon reset, TCSRF is initialized to H'00. Bit 7—Timer Overflow Flag H (OVFH): Bit 7 is a status flag indicating TCFH overflow (H'FF to H'00). This flag is set by hardware and cleared by software. It cannot be set by software. Bit 7: OVFH Description 0 [Clearing conditions] (initial value) After reading OVFH = 1, cleared by writing 0 to OVFH 1 [Setting conditions] Set when the value of TCFH goes from H'FF to H'00 |
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