32186 datasheet(40/1032 Pages) RENESAS

40 / 1032 page

CPU

2-4

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

2.3 Control Registers

2.3.2 Condition Bit Register: CBR (CR1)

The Condition Bit Register (CBR) is derived from the PSW register by extracting its Condition (C) bit. The

value written to the PSW register’s C bit is reflected in this register. The register can only be read. (Writing

to the register with the MVTC instruction is ignored.)

Upon exiting the reset state, the value of CBR is H’0000 0000.

b31

0000000000000000000000000000000

CBR

2.3.3 Interrupt Stack Pointer: SPI (CR2) and User Stack Pointer: SPU (CR3)

The Interrupt Stack Pointer (SPI) and the User Stack Pointer (SPU) retain the address of the current stack

pointer. These registers can be accessed as the general-purpose register R15. R15 switches between

representing the SPI and SPU depending on the value of the Stack Mode (SM) bit in the PSW.

Upon exiting the reset state, the values of the SPI and SPU are undefined.

b31

SPI

b31

SPU

2.3.4 Backup PC: BPC (CR6)

The Backup PC (BPC) is used to save the value of the Program Counter (PC) when an EIT occurs. Bit 31

is fixed to "0."

When an EIT occurs, the register sets either the PC value when the EIT occurred or the PC value for the

next instruction depending on the type of EIT. The BPC value is loaded to the PC when the RTE instruction

is executed. However, the values of the lower 2 bits of the PC are always "00" when returned. (PC always

returns to the word-aligned address.)

Upon exiting the reset state, the value of the BPC is undefined.

b31

BPC

32186 Datasheet(PDF) 40 Page - Renesas Technology Corp