32186 datasheet(20/1032 Pages) RENESAS

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OVERVIEW

1-2

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

1.1 Outline of 32185/32186 Group

The 32185/32186 group (hereafter simply the 32185/32186) belongs to the M32R/ECU series in the M32R

family of Renesas microcomputers. For details about the current development status of the 32185/32186,

please contact your nearest office of Renesas or its distributor.

Table 1.1.1 Product List

Type Name

ROM

RAM

Frequency

Power supply voltage

Temperature Range

capacity

at single-supply

at double-supply

(Note 1)

M32185F4VFP

512 Kbytes

32 Kbytes

80MHz

5V or 3.3V

5V, 3.3V

–40°C to 125°C

M32186F8VFP

1 Mbyte

64 Kbytes

80MHz

5V or 3.3V

5V, 3.3V

–40°C to 125°C

Note 1: This does not guarantee continuous operation and there is a limitation on the length of use (temperature profile).

1.1.1 M32R Family CPU Core with Built-in FPU (M32R-FPU)

(1) Based on a RISC architecture

• The 32185/32186 is a group of 32-bit RISC single-chip microcomputers. The M32R-FPU in this

group of microcomputers incorporates a fully IEEE 754-compliant, single-precision FPU in order to

materialize the common instruction set and the high-precision arithmetic operation of the M32R

CPU. The 32185/32186 products listed in the above table are built around the M32R-FPU and incor-

porate flash memory, RAM and various peripheral functions, all integrated into a single chip.

• The M32R-FPU is constructed based on a RISC architecture. Memory is accessed using load/store

instructions, and various arithmetic/logic operations are executed using register-to-register opera-

tion instructions.

• The M32R-FPU internally contains sixteen 32-bit general-purpose registers. The instruction set con-

sists of 100 discrete instructions in total (83 instructions common to the M32R Family plus 17 FPU

and extended instructions). These instructions are either 16 bits or 32 bits long.

• In addition to the ordinary load/store instructions, the M32R-FPU supports compound instructions

such as Load & Address Update and Store & Address Update. These instructions help to speed up

data transfers.

(2) Six-stage pipelined processing

• The M32R-FPU supports six-stage pipelined instruction processing. Not just load/store instructions

and register-to-register operation instructions, but also floating-point arithmetic instructions and

compound instructions such as Load & Address Update and Store & Address Update are executed

in one CPUCLK period (which is equivalent to 12.5 ns when f(CPUCLK) = 80 MHz).

• Although instructions are supplied to the execution stage in the order in which they were fetched, it

is possible that if the load/store instruction supplied first is extended by wait cycles inserted in

memory access, the subsequent register-to-register operation instruction will be executed before

that instruction. Using such a facility, which is known as the “out-of-order-completion” mechanism,

the M32R-FPU is able to control instruction execution without wasting clock cycles.

(3) Compact instruction code

• The M32R-FPU supports two instruction formats: one 16 bits long, and one 32 bits long. Use of the

16-bit instruction format especially helps to suppress the code size of a program.

• Moreover, the availability of 32-bit instructions makes programming easier and provides higher per-

formance at the same clock speed than in architectures where the address space is segmented. For

example, some 32-bit instructions allow control to jump to an address 32 Mbytes forward or back-

ward from the currently executed address in one instruction, making programming easy.

1.1 Outline of 32185/32186 Group

32186 Datasheet(PDF) 20 Page - Renesas Technology Corp

32186 Datasheet(HTML) 20 Page - Renesas Technology Corp

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