32186 datasheet(16/1032 Pages) RENESAS

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Contents-11

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

CHAPTER 20 OSCILLATOR CIRCUIT

20.1 Oscillator Circuit ............................................................................................................................... 20-2

20.1.1 Example of Oscillator Circuit .................................................................................................... 20-2

20.1.2 XIN Oscillation Stoppage Detection Circuit .............................................................................. 20-3

20.1.3 Oscillation Drive Capability Select Function ............................................................................. 20-5

20.1.4 System Clock Output Function ................................................................................................. 20-7

20.1.5 Oscillation Stabilization Time at Power-On ............................................................................... 20-11

20.2 Clock Generator Circuit .................................................................................................................... 20-12

CHAPTER 21 JTAG

21.1 Outline of JTAG ................................................................................................................................ 21-2

21.2 Configuration of JTAG Circuit ........................................................................................................... 21-3

21.3 JTAG Registers ................................................................................................................................ 21-4

21.3.1 Instruction Register (JTAGIR) .................................................................................................. 21-4

21.3.2 Data Register ........................................................................................................................... 21-5

21.4 Basic Operation of JTAG .................................................................................................................. 21-6

21.4.1 Outline of JTAG Operation ....................................................................................................... 21-6

21.4.2 IR Path Sequence .................................................................................................................... 21-8

21.4.3 DR Path Sequence .................................................................................................................. 21-9

21.4.4 Inspecting and Setting Data Registers ..................................................................................... 21-10

21.5 Boundary Scan Description Language ............................................................................................. 21-11

21.6 Notes on Board Design when Connecting JTAG ............................................................................. 21-12

21.7 Processing Pins when Not Using JTAG ........................................................................................... 21-13

CHAPTER 22 POWER SUPPLY CIRCUIT

22.1 Configuration of Power Supply Circuit .............................................................................................. 22-2

22.2 Power-On Sequence ........................................................................................................................ 22-3

22.2.1 Power-On Sequence when Not Using RAM Backup ................................................................ 22-3

22.2.2 Power-On Sequence when Using RAM Backup ...................................................................... 22-4

22.3 Power-Off Sequence ........................................................................................................................ 22-5

22.3.1 Power-Off Sequence when Not Using RAM Backup ................................................................ 22-5

22.3.2 Power-Off Sequence when Using RAM Backup ...................................................................... 22-6

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