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32186 Datasheet(PDF) 14 Page - Renesas Technology Corp |
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32186 Datasheet(HTML) 14 Page - Renesas Technology Corp |
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14 / 1032 page ![]() Contents-9 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 CHAPTER 14 DIRECT RAM INTERFACE (DRI) 14.1 Outline of Direct RAM Interface (DRI) .............................................................................................. 14-2 14.2 DRI Related Registers ...................................................................................................................... 14-4 14.2.1 DD Input Pin Select Register .................................................................................................... 14-6 14.2.2 DRI Interrupt Related Registers ............................................................................................... 14-7 14.2.3 DRI Transfer Control Register .................................................................................................. 14-13 14.2.4 DRI Special Mode Control Register .......................................................................................... 14-15 14.2.5 DRI Data Capture Control Register .......................................................................................... 14-18 14.2.6 DRI Data Interleave Control Register ....................................................................................... 14-22 14.2.7 DIN Input Event Select Register ............................................................................................... 14-22 14.2.8 DD Input Enable Registers ....................................................................................................... 14-23 14.2.9 DRI Data Capture Event Count Setting Register ...................................................................... 14-25 14.2.10 DRI Capture Event Counter ................................................................................................... 14-26 14.2.11 DRI Transfer Counter ............................................................................................................. 14-27 14.2.12 DRI Address Counters ........................................................................................................... 14-28 14.2.13 DRI Address Reload Registers .............................................................................................. 14-29 14.2.14 DIN Input Processing Control Register .................................................................................. 14-30 14.2.15 DRI Event Counter (DEC) Control Registers ......................................................................... 14-31 14.2.16 DRI Event Counters (DEC Counters) ..................................................................................... 14-36 14.2.17 DRI Event Counter (DEC) Reload Registers .......................................................................... 14-36 14.3 Notes on DRI .................................................................................................................................... 14-37 CHAPTER 15 REAL TIME DEBUGGER (RTD) 15.1 Outline of Real-Time Debugger (RTD) ............................................................................................. 15-2 15.2 Pin Functions of RTD ....................................................................................................................... 15-3 15.3 RTD Related Register ...................................................................................................................... 15-3 15.3.1 RTD Write Function Disable Register ....................................................................................... 15-3 15.4 Functional Description of RTD ......................................................................................................... 15-4 15.4.1 Outline of RTD Operation ......................................................................................................... 15-4 15.4.2 Operation of RDR (Real-time RAM Content Output) ................................................................ 15-4 15.4.3 Operation of WRR (RAM Content Forcible Rewrite) ................................................................ 15-6 15.4.4 Operation of VER (Continuous Monitor) ................................................................................... 15-7 15.4.5 Operation of VEI (Interrupt Request) ........................................................................................ 15-7 15.4.6 Operation of RCV (Recover from Runaway) ............................................................................ 15-8 15.4.7 Method for Setting Specified Address when Using the RTD .................................................... 15-9 15.4.8 Resetting RTD .......................................................................................................................... 15-10 15.5 Typical Connection with Host ........................................................................................................... 15-11 |
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