32186 datasheet(42/1032 Pages) RENESAS

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CPU

2-6

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

0: No underflow exception occurred

R (Note 3)

Underflow Exception Cause Bit

1: An underflow exception occurred. When the bit is set to "1,"

the execution of an FPU operation instruction will clear it to "0."

0: No zero divide exception occurred.

R (Note 3)

Zero Divide Exception Cause Bit

1: A zero divide exception occurred. When the bit is set to "1,"

the execution of an FPU operation instruction will clear it to "0."

0: No overflow exception occurred.

R (Note 3)

Overflow Exception Cause Bit

1: An overflow exception occurred. When the bit is set to "1,"

the execution of an FPU operation instruction will clear it to "0."

0: No invalid operation exception occurred.

R (Note 3)

Invalid Operation Exception Cause Bit

1: An invalid operation exception occurred. When the bit is set to "1,"

the execution of an FPU operation instruction will clear it to "0."

30, 31

00: Round to nearest

Rounding Mode Selection Bit

01: Round toward Zero

10: Round toward + Infinity

11: Round toward – Infinity

Note 1: The phrase “If EIT processing unexecuted” means whenever one of the exceptions occurs, enable bits 17 to 21 are set

to "0" which masks the EIT processing so that it cannot be executed. If two exceptions occur at the same time and their

corresponding exception enable bits are set differently (one enabled, and the other masked), EIT processing is

executed. In this case, these two flags do not change state regardless of the enable bits settings.

Note 2: If a denormalized number is given to the operand when DN = "0," an unimplemented exception occurs.

Note 3: This bit is cleared by writing "0." Writing "1" has no effect (the bit retains the value it had before the write).

2.3 Control Registers

32186 Datasheet(PDF) 42 Page - Renesas Technology Corp