32186 datasheet(633/1032 Pages) RENESAS

633 / 1032 page

CAN MODULE

13-23

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

13.2.1 CAN Bus Mode Control Register

CAN Bus Mode Control Register (CANBUSCR)

<Address: H’0080 052A>

123456

CBUSSELP

00000000

CBUSSEL

Bit Name

Function

0–5

No function assigned. Fix to "0."

CBUSSELP

(CBUSSEL write control bit)

CBUSSEL

0: CAN0/CAN1 CAN bus independent

(CAN bus mode select bit)

1: CAN0/CAN1 CAN bus share

Note: • Change this register value with FRST bits (inside the CAN control register) of both CAN0 & CAN1 set at "1."

By setting the CBUSSEL bit to "1," two CAN modules are internally connected, which can be used artificially as

64-slot CAN.

• When CBUSSEL = 0

CAN0 and CAN1 use CTX0/CRX0 and CTX1/CRX1 as a pin, respectively.

• When CBUSSEL = 1

Both CAN0 and CAN1 use CTX0/CRX0 as a pin.

When CAN0 / CAN1 CAN bus share (CBUSSEL = 1 ) are described below.

• Do not select CTX1/CRX1 with the port operation mode register/port peripheral function select register.

• When both CANs generate a transmit request and both CAN0/CAN1 in operation, the output of CAN

having ID with higher priority corresponds to CTX0 output due to internal arbitration. Also, the CAN lost in

arbitration then operates as a receiving node, but no dominant level is output in the ACK field.

• In case where both CAN0 and CAN1 are operated, the CANs do not perform operation as error passive node

as viewed from the outside unless the both of them are in error passive state. The CANs do not perform

operation as error bus off node as viewed from the outside unless the both of them are in error bus off state.

Therefore, consideration is required such as making both CANs error states the same in software.

• Do not set the transmit slot that has the same ID in both CAN0 and CAN1.

• When both CAN0 and CAN1 are being operated, if there is a slot which completes one CAN transmission

and meets the receiving conditions by the other CAN, "the other CAN" stores the received data.

When set this resiter, procedure is described below.

1. Write "1" in CBUSSEL write control bit (CBUSSELP)

2. Following 1. write "0" in CBUSSEL write control bit (CBUSSELP) , write "0" or "1" in CBUSSEL output

prohibition select bit (CBUSSEL)

Note: • If theare are writing cycles from CPU, DMA, SDI (tool), NBD to any other area between 1 and 2, the

continuous setting ( A pair of two consecutive is 1 set for writing operation) is disabled and the writing

value is not reflected. Therefore, disable interrupts and DMA transfers before setting. However the

writing cycle from RTD and DRI are not effected.

13.2 CAN Module Related Registers

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