4502 datasheet(121/214 Pages) RENESAS

121 / 214 page

2.1 I/O pins

2-4

Rev.2.01

Feb 02, 2005

4502 Group

APPLICATION

REJ09B0193-0201

(5)

Port D

D0–D5 are six independent I/O ports.

Also, as for ports D2 and D3, its key-on wakeup function is switched to ON/OFF by the register K22

and K23, and its pull-up transistor function is switched to ON/OFF by the register PU22 and PU23.

s Input/output of port D

Each pin of port D has an independent 1-bit wide I/O function. For I/O of ports D0–D5, select one

of port D with the register Y of the data pointer first.

q Data input to port D

Set the output latch of specified port Di (i = 0 to 5) to “1” with the SD instruction.

When the output latch is set to “0,” “L” level is input.

When the SZD instruction is executed, if the port specified by register Y is “0,” the next

instruction is skipped. If it is “1,” the next instruction is executed.

q Data output from port D

Set the output level to the output latch with the SD and RD instructions.

The state of pin enters the high-impedance state when the SD instruction is executed.

The states of all port D enter the high-impedance state when the CLD instruction is executed.

The state of pin becomes “L” level when the RD instruction is executed.

The output structure is an N-channel open-drain.

Notes 1: When the SD and RD instructions are used, do not set “01102” or more to register Y.

2: Port D2 is also used as Port C. Accordingly, when using port D2, set the output latch to

“1” with the SCP instruction.

3: Port D3 is also used as Port K. Accordingly, when using port D3, set the output latch to

“1” with the OKA instruction.

4502 Datasheet(PDF) 121 Page - Renesas Technology Corp