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4502 Datasheet(PDF) 143 Page - Renesas Technology Corp |
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4502 Datasheet(HTML) 143 Page - Renesas Technology Corp |
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143 / 214 page ![]() 2.3 Timers 2-26 Rev.2.01 Feb 02, 2005 4502 Group APPLICATION REJ09B0193-0201 (4) Timer operation: timer start by external input Outline: The constant period can be measured by external input. Specifications: System clock frequency f(XIN) = 4 MHz and timer 1 operates by INT input as a trigger and an interrupt occurs after 1 ms. Figure 2.3.6 shows the setting example of timer start. (5) Watchdog timer Watchdog timer provides a method to reset the system when a program run-away occurs. Accordingly, when the watchdog timer function is set to be valid, execute the WRST instruction at a certain period which consists of timer 16-bit timers’ 65534 counts or less (execute WRST instruction at a cycle of 65534 machine cycles or less). Outline: Execute the WRST instruction in 16-bit timer’s 65534 counts at the normal operation. If a program runs incorrectly, the WRST instruction is not executed and system reset occurs. Specifications: System clock frequency f(XIN) = 4.0 MHz is used, and program run-away is detected by executing the WRST instruction in 49 ms. Figure 2.3.2 shows the watchdog timer function, and Figure 2.3.7 shows the example of watchdog timer. Fig. 2.3.2 Watchdog timer function 65534 count (Note) Value of 16-bit timer (WDT) WDF1 flag ➂ WRST instruction executed (skip executed) RESET pin output WDF2 flag ➄ System reset ➀ Reset released ➀ After system is released from reset (= after program is started), timer WDT starts count down. ➁ When timer WDT underflow occurs, WDF1 flag is set to “1.” ➂ When the WRST instruction is executed, WDF1 flag is cleared to “0,” the next instruction is skipped. ➃ When timer WDT underflow occurs while WDF1 flag is “1,” WDF2 flag is set to “1” and the watchdog reset signal is output. ➄ The output transistor of RESET pin is turned “ON” by the watchdog reset signal and system reset is executed. Note: The number of count is equal to the number of machine cycle because the count source of watchdog timer is the instruction clock. FFFF16 000016 ➁ ➁ ➃ |
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