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4502 Datasheet(PDF) 173 Page - Renesas Technology Corp

Part # 4502
Description  4-BIT CISC SINGLE-CHIP MICROCOMPUTER 4500 SERIES
PDF  214 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

4502 Datasheet(HTML) 173 Page - Renesas Technology Corp

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3.1 Electrical characteristics
3-3
4502 Group
APPENDIX
Rev.2.01
Feb 02, 2005
REJ09B0193-0201
3.1.2 Recommended operating conditions
Table 3.1.2 Recommended operating conditions 1
(Ta = –20 °C to 85 °C, VDD = 2.7 to 5.5 V, unless otherwise noted)
Symbol
VDD
VRAM
VSS
VIH
VIH
VIH
VIH
VIH
VIL
VIL
VIL
VIL
IOL(peak)
IOL(peak)
IOL(peak)
IOL(peak)
IOL(avg)
IOL(avg)
IOL(avg)
IOL(avg)
ΣIOL(avg)
Parameter
Supply voltage
RAM back-up voltage
Supply voltage
“H” level input voltage
“H” level input voltage
“H” level input voltage
“H” level input voltage
“H” level input voltage
“L” level input voltage
“L” level input voltage
“L” level input voltage
“L” level input voltage
“L” level peak output current
“L” level peak output current
“L” level peak output current
“L” level peak output current
“L” level average output current
“L” level average output current
“L” level average output current
“L” level average output current
“L” level total average current
Notes 1: System is in the reset state when the value is the detection voltage of the voltage drop detection circuit or less.
2: The voltage drop detection circuit is operating in the RAM back-up with the POF instruction (system enters into the reset state when the value is
VRST or less). In the RAM back-up mode with the POF2 instruction, the voltage drop detection circuit stops.
3: The average output current (IOH, IOL) is the average value during 100 ms.
Unit
Conditions
High-speed mode
Middle-speed mode
Low-speed mode
Default mode
(at RAM back-up mode with the POF2
instruction)
P0, P1, P2, P3, D2, D3, XIN
D0, D1, D4, D5
RESET
C, K
CNTR, INT
P0, P1, P2, P3, D0–D5, XIN
C, K
RESET
CNTR, INT
P2, P3, RESET
D0, D1
D2/C, D3/K, D4, D5
P0, P1
P2, P3, RESET (Note 3)
D0, D1 (Note 3)
D2/C, D3/K, D4, D5 (Note 3)
P0, P1 (Note 3)
P2, D, RESET
P0, P1, P3
Max.
5.5
VDD
12
VDD
VDD
VDD
VDD
0.2VDD
0.16VDD
0.3VDD
0.15VDD
10
40
24
24
5.0
30
15
12
80
80
Limits
Min.
2.7
(Note 1)
1.8 (Note 2)
0.8VDD
0.8VDD
0.85VDD
0.5VDD
0.7VDD
0.85VDD
0
0
0
0
Typ.
0
f(XIN)
≤ 4.4 MHz
VDD = 4.0 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 5.0 V
VDD = 5.0 V
VDD = 5.0 V
VDD = 5.0 V
VDD = 5.0 V
VDD = 5.0 V
VDD = 5.0 V
VDD = 5.0 V
V
V
V
V
V
V
V
V
V
V
V
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
4.4
f [MHz]
f [MHz]
Ceramic resonator and high-speed mode selected
External clock input (ceramic resonator selected)
Recommended operating
condition
4.2
2.7
5.5
VDD[V]
VRST
(Note)
3.2
4.2
2.7
5.5
VDD[V]
VRST
(Note)
Recommended operating
condition
It shows the electrical characteristics range of detected voltage
for voltage drop detection circuit.
System reset occurs when the supply voltage is under
the detected voltage for voltage drop detection circuit.
Note:



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