4502 datasheet(169/214 Pages) RENESAS

169 / 214 page

2.8 Oscillation circuit

2-52

Rev.2.01

Feb 02, 2005

4502 Group

APPLICATION

REJ09B0193-0201

2.8.2 Oscillation operation

System clock is supplied to CPU and peripheral device as the standard clock for the microcomputer

operation. For the 4502 Group, the clock supplied from the on-chip oscillator (internal oscillator) or the

ceramic resonance circuit, RC oscillation circuit is selected from the high-speed mode (f(XIN)), middle-

speed mode (f(XIN)/2), low-speed mode (f(XIN)/4) or default mode (f(XIN)/8) with the register MR.

Figure 2.8.5 shows the structure of the clock control circuit.

Fig. 2.8.5 Structure of clock control circuit

MR3, MR2

Q S

CRCK instruction

Q S

CMCK

instruction

Q S

RESET pin

XOUT

XIN

Key-on wakeup signal

Instruction clock

Counter

Wait time (Note 2)

control circuit

Program

start signal

RC oscillation circuit

Division circuit

divided by 8

divided by 4

divided by 2

Internal clock

generation circuit

(divided by 3)

Notes 1: System operates by the on-chip oscillator clock (f(RING)) until the CMCK or CRCK instruction

is executed after system is released from reset.

2: The wait time control circuit is used to generate the time required to stabilize the f(XIN) oscillation.

After the certain oscillation stabilizing wait time elapses, the program start signal is output.

This circuit operates when system is released from reset or returned from RAM back-up.

System clock

On-chip oscillator

(internal oscillator)

(Note 1)

Multiplexer

Ceramic resonator

circuit

POF or

EPOF instruction + POF2

instruction

4502 Datasheet(PDF) 169 Page - Renesas Technology Corp

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