7721 datasheet(345/577 Pages) RENESAS

345 / 577 page

DMA CONTROLLER

13-66

13.6 Repeat transfer mode

7721 Group User’s Manual

13.6.2 Operation in repeat transfer mode

Figure 13.6.5 shows the operation flowchart of the repeat transfer mode, and Figure 13.6.6 shows a timing

diagram of the repeat transfer mode (burst transfer mode).

For the cycle-steal transfer mode, refer to the following:

• All transfers except for the last 1-unit transfer: Figure 13.8.12

• Last 1-unit transfer: Figure 13.8.13

Also, refer to section “13.2.1 Bus access control circuit” for the bus request sampling during transfer.

DMAi request bit

← 0

1-unit transfer

(Only in cycle-steal transfer mode)

(Refer to section “13.4 Operation.”)

Burst·Edge

: In burst transfer mode (edge sense)

Burst·Level·L

: In burst transfer mode (level sense) with DMAREQi pin’s input level = L

Burst·Level·H

: In burst transfer mode (level sense) with DMAREQi pin’s input level = H

Cycle-steal·Requested

: In cycle-steal transfer mode with any request of DMA0–3

Cycle-steal·No request

: In cycle-steal transfer mode with no request of DMA0–3

DMAi request bit ?

Burst·Level·H

Cycle-steal·No request

Burst·Edge

Burst·Level·L

Cycle-steal·Requested

Fig. 13.6.5 Operation flowchart of repeat transfer mode

7721 Datasheet(PDF) 345 Page - Renesas Technology Corp