7721 datasheet(347/577 Pages) RENESAS

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DMA CONTROLLER

13-68

13.7 Array chain transfer mode

7721 Group User’s Manual

13.7 Array chain transfer mode

This mode is used to transfer several blocks of data. According to the information of each block stored in

memory area (Note), several blocks of data are transferred. All of the transfer parameters must be located

in series. Table 13.7.1 lists the specifications of the array chain transfer mode, and Figure 13.7.1 shows the

Note: Each of the following information is called “transfer parameter”: transfer start addresses of transfer

source and destination, and transfer data’s byte number.

Table 13.7.1 Specifications of array chain transfer mode

Item

Transfer parameter memory

Condition of normal termination

Conditions of forced termination

Interrupt request generation timing

Functions of registers

Performance specifications

Required.

q In 2-bus cycle transfer: 12 bytes per one block

(transfer source’s transfer start address, transfer destination’s transfer

start address, transfer data’s byte number)

q In 1-bus cycle transfer: 8 bytes per one block

(from memory to I/O: transfer source’s transfer start address, transfer

data’s byte number)

(from I/O to memory: transfer destination’s transfer start address,

transfer data’s byte number)

TCRi latch = 0 and TCRi = 0

___

q Falling edge of the TC pin’s input from “H” to “L”

___

(when the TC pin validity bit = “1”)

q Write “0” to the DMAi enable bit

At normal termination

SARi latch: Indicates the transfer parameter memory’s start address of

the next block.

SARi: Indicates the address of the next transfer source.

DARi latch: Not used.

DARi: Indicates the address of the next transfer destination.

TCRi latch: Indicates the number of remaining transfer blocks.

TCRi: Indicates the number of remaining transfer bytes.

___

pin validity bit: Bit 1 at address 6816

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