7721 datasheet(493/577 Pages) RENESAS

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APPENDIX

Appendix 3. Control registers

7721 Group User’s Manual

17–30

DRAM control register

0 0 0 0 : No DRAM area

0 0 0 1 : F0000016–FFFFFF16 (1 Mbyte)

0 0 1 0 : E0000016–FFFFFF16 (2 Mbytes)

0 0 1 1 : D0000016–FFFFFF16 (3 Mbytes)

0 1 0 0 : C0000016–FFFFFF16 (4 Mbytes)

0 1 0 1 : B0000016–FFFFFF16 (5 Mbytes)

0 1 1 0 : A0000016–FFFFFF16 (6 Mbytes)

0 1 1 1 : 90000016–FFFFFF16 (7 Mbytes)

1 0 0 0 : 80000016–FFFFFF16 (8 Mbytes)

1 0 0 1 : 70000016–FFFFFF16 (9 Mbytes)

1 0 1 0 : 60000016–FFFFFF16 (10 Mbytes)

1 0 1 1 : 50000016–FFFFFF16 (11 Mbytes)

1 1 0 0 : 40000016–FFFFFF16 (12 Mbytes)

1 1 0 1 : 30000016–FFFFFF16 (13 Mbytes)

1 1 1 0 : 20000016–FFFFFF16 (14 Mbytes)

1 1 1 1 : 10000016–FFFFFF16 (15 Mbytes)

Bit

Bit name

Functions

At reset

6 to 4

DRAM area select bits

DRAM validity bit (Note)

0 : Invalid (P104–P107 pins function

as programmable input ports. A0–

A7 pins function as address

output pins. Refresh timer stops

counting.)

1 : Valid (P104–P107 pins function as

CAS, RAS, MA8, and MA9. A0–A7

function as MA0–MA7. Refresh

timer starts counting.)

DRAM control register (Address 6416)

–

Nothing is assigned.

The value is “0” at reading.

b3 b2 b1 b0

Note: Set the refresh timer (address 6616) before setting this bit to “1.”

Refresh timer

Refresh timer (Address 6616)

Functions

Bit

At reset

7 to 0 These bits can be set to “0116” to “FF16.”

Assuming that the set value = n, this register divides f16 by

(n + 1).

Undefined

Note: Use the LDM or STA instruction for writing to this register.

Do not set this register to “0016.”

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