7721 datasheet(501/577 Pages) RENESAS

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APPENDIX

Appendix 3. Control registers

7721 Group User’s Manual

17–38

DMAi mode register L

Bit

Bit name

At reset

Functions

DMA0 mode register L (Address 1FCC16)

DMA1 mode register L (Address 1FDC16)

DMA2 mode register L (Address 1FEC16)

DMA3 mode register L (Address 1FFC16)

Note: When the external data bus has a width of 8 bits and 1-bus cycle transfer is selected, set

bit 0 to “1.”

0 : 16 bits

1 : 8 bits

0 : 2-bus cycle transfer

1 : 1-bus cycle transfer

0 : Burst transfer mode

1 : Cycle-steal transfer mode

0 0 : Fixed

0 1 : Forward

1 0 : Backward

1 1 : Do not select.

Number-of-unit-transfer-bits

select bit (Note)

Transfer method select bit

Transfer mode select bit

Fix this bit to “0.”

Transfer source address

direction select bits

Transfer destination address

direction select bits

0 0 : Fixed

0 1 : Forward

1 0 : Backward

1 1 : Do not select.

b5b4

b7b6

DMAi mode register H

Bit

Bit name

At reset

Functions

DMA0 mode register H (Address 1FCD16)

DMA1 mode register H (Address 1FDD16)

DMA2 mode register H (Address 1FED16)

DMA3 mode register H (Address 1FFD16)

Notes 1: Set bit 0 to “0” in 2-bus cycle transfer.

2: Bits 4 and 5 are valid to the external and internal areas. However, DRAM area is

always handled with “Wait” regardless of the contents of these bits.

The wait bit (bit 2 at address 5E16) is invalid in DMA transfer.

0 : From memory to I/O

1 : From I/O to memory

Refer to “Fig.13.2.7.”

Transfer direction select bit

(Used in 1-bus cycle transfer) (Note 1)

I/O connection select bit

(Valid in 1-bus cycle transfer)

Fix these bits to “0.”

Transfer source wait bit (Note 2)

Continuous transfer mode select

bits

0 0 : Single transfer

0 1 : Repeat transfer

1 0 : Array chain transfer

1 1 : Link array chain transfer

b7b6

Transfer destination wait bit (Note 2)

0 : Wait

1 : No Wait

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