7721 datasheet(532/577 Pages) RENESAS

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APPENDIX

7721 Group User’s Manual

17–69

Appendix 9. 7721 Group Q & A

Interrupt

Suppose that there is a routine which should not accept one certain interrupt request. (The other

interrupt request are acceptable).

Although when the interrupt priority level select bits for the above interrupt are set to “0002,” in other

words, when this interrupt is set to be disabled, this interrupt request is actually accepted immediately

after change of the priority level. Why did this occur and what should I do about it?

As for the change of the interrupt priority level, when the following are met, the microcomputer may

pretend to accept an interrupt request immediately after this interrupt is set to be disabled:

•The next instruction (in the above example, it is the LDA instruction) is already stored into a instruc-

tion queue buffer for the BIU.

•Conditions for accepting the instruction which should not be accepted are satisfied immediately

before the next instruction in the instruction queue buffer is executed.

When writing to a memory or an I/O, the CPU passes the address and data to the BIU. Then, the

CPU executes the next instruction in the instruction queue buffer while the BIU is writing data into

the actual address. Detection of interrupt priority level is performed at the beginning of each instruc-

tion.

In the above case, the CPU executes the next instruction before the BIU completes the change of

the interrupt priority level. Therefore, when the interrupt priority level is detected synchronously with

the execution of the next instruction, the interrupt priority level before the change is detected and its

interrupt request is accepted.

(1/2)

Interrupt request is

accepted

this

interval

LDM #00H, XXXIC ; Writes “0002” to interrupt priority level select bits.

; Clears interrupt request bit to “0.”

LDA A,DATA

; Instruction at the beginning of the routine which

should not accept one certain interrupt request.

Previous instruction

executed

(Instruction prefetched)

CPU operation

BIU operation

Interrupt priority detection time

Sequence of execution

Interrupt priority level select bits set

Change of interrupt priority levels

completed

Interrupt request accepted

Interrupt request generated

LDM instruction

executed

LDA instruction

executed

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