7721 datasheet(560/577 Pages) RENESAS

560 / 577 page

7721 Group User’s Manual

17–97

Appendix 11. Electrical characteristics

APPENDIX

DMAC switching characteristics (VCC = 5 V ±10 %, VSS = 0 V, Ta = –20 to 85 °C, f(XIN) = 25 MHz,

unless otherwise noted)

Note: The limits depend on f(XIN). Table 6 lists calculation formulas for the limits.

Limits

tsu(DRQ-φ1)

tw(DRQ)

td(φ1–STi)

td(φ1–DAK)

td(AL–E)

td(E–DHQ)

tpxz(E–DHZ)

td(AM–E)

td(E–DLQ)

tpxz(E–DLZ)

td(AH–E)

td(ALE–E)

tw(ALE)

td(BHE–E)

td(BLE–E)

td(R/W–E)

th(E–AL)

th(ALE–AM)

th(E–DHQ)

tpzx(E–DHZ)

th(E–AM)

th(ALE–AH)

th(E–DLQ)

tpzx(E–DLZ)

th(E–BHE)

th(E–BLE)

th(E–R/W)

tw(EL)

td(data)

td(φ1–TC)

tw(TC)

tsu(TCIN)

tw(TCIN)

________

DMAREQi input setup time

________

DMAREQi input pulse width

ST0, ST1 output delay time

________

DMAACKi output delay time

Address low-order output delay time

Data high-order output delay time (BYTE = “L”)

Data high-order floating start delay time (BYTE = “L”)

Address middle-order output delay time

Data low-order output delay time

Data low-order floating start delay time

Address high-order output delay time

ALE output delay time

ALE pulse width

____

BHE output delay time

____

BLE output delay time

R/W output delay time

Address low-order hold time

Address middle-order hold time (BYTE = “L”)

Data high-order hold time (BYTE = “L”)

Data high-order floating release delay time (BYTE = “L”)

Address middle-order hold time (BYTE = “H”)

Address high-order hold time

Data low-order hold time

Data low-order floating release delay time

____

BHE hold time

____

BLE hold time

R/W hold time

E pulse width

Copy delay time

___

TC output delay time

___

TC output pulse width

___

TC input setup time

___

TC input pulse width

Max.

Parameter

Symbol

Min.

Unit

(Note)

Note: Figures 13 and 14 show the test circuits.

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