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7721 Datasheet(PDF) 558 Page - Renesas Technology Corp |
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7721 Datasheet(HTML) 558 Page - Renesas Technology Corp |
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558 / 577 page  7721 Group User’s Manual 17–95 Appendix 11. Electrical characteristics APPENDIX DRAM control switching characteristics (VCC = 5 V ± 10 %, VSS = 0 V, Ta = –20 to 85 °C, f(XIN) = 25 MHz, unless otherwise noted) Note: The limits depend on f(XIN). Table 5 lists calculation formulas for the limits. Limits tw(RASL) tw(CASL) tw(RASH) td(RAS–CAS) td(RA–RAS) th(RAS–RA) td(CA–CAS) th(CAS–CA) td(R/W–RAS) th(CAS–R/W) td(E–CA) td(E–RASL) td(E–CASL) td(E–RASH) td(E–CASH) ____ RAS low–level pulse width ____ CAS low–level pulse width ____ CAS high–level pulse width ____ ____ RAS–CAS delay time ____ Row address delay time before RAS ____ Row address hold time after RAS ____ Column address delay time before CAS ____ Column address hold time after CAS __ ____ R/W delay time before RAS __ ____ R/W hold time after CAS __ Column address delay time after E’s low level ____ __ RAS delay time after E’s low level ____ __ CAS delay time after E’s low level ____ __ RAS delay time after E’s high level ____ __ CAS delay time after E’s high level Max. Parameter Read Symbol Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note: Figure 13 shows the test circuit. Limits tw(RASL) tw(CASL) tw(RASH) td(RAS–CAS) td(RA–RAS) th(RAS–RA) td(CA–CAS) th(CAS–CA) td(R/W–RAS) th(CAS–R/W) td(E–RASL) td(E–CASL) td(E–RASH) td(E–CASH) ____ RAS low–level pulse width ____ CAS low–level pulse width ____ CAS high–level pulse width ____ ____ RAS–CAS delay time ____ Row address delay time before RAS ____ Row address hold time after RAS ____ Column address delay time before CAS ____ Column address hold time afrer CAS __ ____ R/W delay time before RAS __ ____ R/W hold time after CAS ____ __ RAS delay time after E’s low level ____ __ CAS delay time after E’s low level ____ __ RAS delay time after E’s high level ____ __ CAS delay time after E’s high level Max. Parameter Write Symbol Min. 120 55 60 60 5 18 10 60 18 18 80 0 0 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) 30 115 20 20 Note: Figure 13 shows the test circuit. Limits tw(RASL) tw(CASL) td(CAS–RAS) th(RAS–CAS) ____ RAS low–level pulse width ____ CAS low–level pulse width ____ ___ CAS–RAS delay time ____ ____ CAS hold time after RAS Max. Parameter Refresh state Symbol Min. 120 55 17.5 17.5 Unit ns ns ns ns (Note) (Note) (Note) (Note) Note: Figure 13 shows the test circuit. 65 30 77.5 20 20 Min. 120 92.5 60 28 5 18 5 100 18 18 0 0 |
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