7721 datasheet(555/577 Pages) RENESAS

555 / 577 page

7721 Group User’s Manual

17–92

APPENDIX

Appendix 11. Electrical characteristics

Microprocessor mode : with Wait

Note: The limits depend on f(XIN). Table 4 lists calculation formulas for the limits.

Limits

tw(H)

tw(L)

tsu(PiD–E)

th(E–PiD)

External clock input cycle time

External clock input high-level pulse width

External clock input low-level pulse width

External clock input rising time

External clock input falling time

Port Pi input setup time (i = 4–10)

Port Pi input hold time (i = 4–10)

Max.

Parameter

Timing requirements (VCC = 5 V ± 10 %, VSS = 0 V, Ta = –20 to 85 °C, f(XIN) = 25 MHz, unless otherwise noted)

Symbol

Min.

Unit

Limits

Max.

Parameter

Switching characteristics (VCC = 5 V ± 10 %, VSS = 0 V, Ta = –20 to 85 °C, f(XIN) = 25 MHz, unless otherwise noted)

Symbol

Min.

135

Unit

130

135

130

135

Note: Figure 13 shows the test circuit.

(Note)

td(E-PiQ)

td(AL–E)

td(E–DHQ)

tpxz(E–DHZ)

td(AM–E)

td(AM–ALE)

td(E–DLQ)

tpxz(E–DLZ)

td(AH–E)

td(AH–ALE)

td(ALE–E)

tw(ALE)

td(BHE–E)

td(BLE–E)

td(R/W–E)

td(E–φ1)

th(E–AL)

th(ALE–AM)

th(E–DHQ)

tpzx(E–DHZ)

th(E–AM)

th(ALE–AH)

th(E–DLQ)

tpzx(E–DLZ)

th(E–BHE)

th(E–BLE)

th(E–R/W)

tw(EL)

tsu(A–DL)

tsu(ALE–DL)

tsu(A–DH)

tsu(ALE–DH)

Port Pi data output delay time

Address low-order output delay time

Data high-order output delay time (BYTE = “L”)

Data high-order floating start delay time (BYTE = “L”)

Address middle-order output delay time

Data low-order output delay time

Data low-order floating start delay time

Address high-order output delay time

ALE output delay time

ALE pulse width

____

BHE output delay time

____

BLE output delay time

R/W output delay time

φ1 output delay time

Address low-order hold time

Address middle-order hold time (BYTE = “L”)

Data high-order hold time (BYTE = “L”)

Data high-order floating release delay time (BYTE = “L”)

Address middle-order hold time (BYTE = “H”)

Address high-order hold time

Data low-order hold time

Data low-order floating release delay time

____

BHE hold time

____

BLE hold time

R/W hold time

E pulse width

Data low-order setup time after address stabilization

Data low-order setup time after rising of ALE

Data high-order setup time after address stabilization

Data high-order setup time after rising of ALE

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