7721 datasheet(282/577 Pages) RENESAS

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7721 Group User’s Manual

13-3

DMA CONTROLLER

13.1.2 Bus use priority levels

The bus use priority levels are fixed by hardware as follows:

DRAMC

Hold function

DMAC >

CPU

(DRAM refresh)

Because DMAC has the third priority, it actually operates as follows:

• When DRAM refresh request or Hold request is generated during DMA transfer

After the transfer of one transfer unit (8-bit or 16-bit data), which is being performed at that time, is

complete, DMAC relinquishes the bus to a DRAM refresh or a Hold function.

When DMAC regains the right to use bus after the DRAM refresh ends or the Hold state is removed,

DMA transfer is restarted at the following address.

• When DMA request is generated during DRAM refresh or in Hold state

DMAC gains the right to use bus after the DRAM refresh ends or the Hold state is removed.

• When DMA request is generated while CPU uses bus

Upon end of the bus cycle, DMAC gains the right to use bus if any DRAM refresh request or Hold

request is not generated at that time.

If a DRAM refresh request or a Hold request is generated when the bus cycle ends, DMAC gains

the right to use bus after the DRAM refresh ends or the Hold state is removed.

For details, refer to section “13.2.1 Bus access control circuit” and bus request sampling signals in

timing diagrams.

13.1.3 Modes

DMAC has the following transfer methods and modes. Because these methods and modes are independent

each other, any combination between them is selectable.

(1)

Data transfer method

s 2-bus cycle transfer

This is a method used to transfer data between memories. A DMA transfer consumes 2 cycles: a

read and a write cycle of data.

For details, refer to section “13.4.1 2-bus cycle transfer.”

s 1-bus cycle transfer

This is a method used to transfer data between a memory and an I/O. A read and write of data

is carried out at the same time (in 1-bus cycle), so that high-speed transfer can be accomplished.

For details, refer to section “13.4.2 1-bus cycle transfer.”

(2)

Transfer unit

s 8-bit transfer

A minimum unit of DMA transfer is 8 bits; that is, an 8-bit data is transferred for one DMA request

in the cycle-steal transfer mode.

In the burst transfer mode, if a DRAM refresh request or a Hold request is generated during DMA

___

transfer, or if TC input is driven from “H” to “L” to force DMA transfer into termination, DMAC

relinquishes the bus after completion of 8-bit data transfer which is being performed at that time.

s 16-bit transfer

A minimum unit of DMA transfer is 16 bits; that is, a 16-bit data is transferred for one DMA request

in the cycle-steal transfer mode.

In the burst transfer mode, if a DRAM refresh request or a Hold request is generated during DMA

___

transfer, or if TC input is driven from “H” to “L” to force DMA transfer into termination, DMAC

relinquishes the bus after completion of 16-bit data transfer which is being performed at that time.

13.1 Overview

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