7721 datasheet(283/577 Pages) RENESAS

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7721 Group User’s Manual

13-4

DMA CONTROLLER

(3)

Transfer modes

s Burst transfer mode

When once a DMA request is accepted in this mode, an entire batch of data is transferred. Neither

is the right to use bus returned to the CPU, nor the DMA request of the channel with the higher

________

priority is accepted until the transfer is complete. However, if an external source (DMAREQi) is

selected as a DMA request source with the level sense selected, DMA transfer is performed when

_________

the DMAREQi pin’s input level is “L,” and the right to use bus is returned to the CPU when the

_________

DMAREQi

pin’s input level is “H.” Even in this case, any DMA request of the other channels is not

accepted until the entire batch of data has been transferred.

For details, refer to section “13.4.3 Burst transfer mode.”

s Cycle-steal transfer mode

For each DMA request, 1 transfer unit of data is transferred. (Hereafter, transferring 1-transfer-unit

data, which is 8-bit or 16-bit data in the M37721, is called “1-unit transfer.”)

When 1-unit transfer is complete and another DMA request (including that of other channels) is not

generated, the DMAC relinquishes the right to use bus to the CPU.

In the cycle-steal transfer mode, all of the DMA request sources are available.

For details, refer to section “13.4.4 Cycle-steal transfer mode.”

Figure 13.1.1 shows the outline of the DMA transfer modes.

s Burst transfer mode (External source (DMAREQi), level sense)

s Burst transfer mode (Edge sense)

Right to use bus

(Transfer of entire batch of data)

CPU

DMAi

CPU

DMAi

DMAREQi input

CPU

DMAi

CPU

DMA1

DMA0

CPU

Right to use bus

s Cycle-steal transfer mode

DMA0 request is accepted.

DMA1 request is accepted.

DMAi request is accepted.

(One transfer unit)

13.1 Overview

Fig. 13.1.1 Outline of DMA transfer modes

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