7721 datasheet(287/577 Pages) RENESAS

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7721 Group User’s Manual

13-8

DMA CONTROLLER

Bus request sampling timing

After completion of a DRAM refresh cycle

Every 1 cycle of

All except the following

At the end of each block

All except the following

At the end of each block

(except the last block)

At the end of the last block

At an array state

When an instruction is

fetched into queue buffer

At a read from or a write into

memory

While CPU does not use bus

The BUS REQUEST signal is sampled at a break in bus use. Table 13.2.3 and Figure 13.2.3 shows the

timings of bus request sampling. Also, bus request sampling signals are shown in them.

Table 13.2.3 Bus request sampling timing

13.2 Block description

After completion of 1-unit transfer

After 1-unit transfer and terminate-processing (3 cycles

φ) etc. are performed sequentially

After completion of 1-unit transfer

s During transfer in burst transfer mode

After the last 1-unit transfer of 1 block, the subsequent

3 cycles of

φ, and a read of the first 2 bytes in the

array state of the next block are performed sequentially

s During transfer in cycle-steal transfer mode

After the last 1-unit transfer of 1 block and the

subsequent 3 cycles of

φ are performed sequentially

After 1-unit transfer and terminate-processing (3 cycles

φ) are performed sequentially

After a read of 2 bytes of a transfer parameter

After completion of 1 bus cycle

After completion of 1 bus cycle, or after completion of

the second bus cycle if a 16-bit data is accessed in a

unit of 8 bits (Note 2).

Every 1 cycle of

Bus user

DRAM refresh

Hold

DMAC

CPU

S/R

(Note 1)

Array/

Link

(Note 1)

Notes 1: S = Single transfer mode, R = Repeat transfer mode, Array = Array chain transfer mode, Link

= Link array chain transfer mode

2: This applies when the data bus width is 8 bits or when memory is accessed starting at an odd

address.

If a DRAM refresh request or a Hold request is generated during a data transfer in the burst transfer mode,

the request is accepted at the above-mentioned bus request sampling. Another DMA request (including that

of other channels) cannot be accepted until the DMA transfer which is in progress normally terminates or

is forced into termination.

If a DRAM refresh request, a Hold request or another DMA request (including that of other channels) is

generated during a data transfer in the cycle-steal transfer mode, the bus request with the highest priority

is accepted at the above-mentioned bus request sampling. (If only several DMA requests are generated,

the request of the channel whose priority is highest is accepted.)

If any bus request is not generated at the above-mentioned bus sampling, the right to use bus is relinquished

to the CPU.

Note that no DMA request is accepted in array states.

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