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7721 Group User’s Manual

13-7

DMA CONTROLLER

13.2 Block description

13.2.1 Bus access control circuit

In the M37721, the bus is used by DRAMC, Hold function, DMAC, and CPU.

When each request of DRAM refresh, Hold, and DMA is generated, each of DRAMC, Hold function, and

DMAC issues its bus request to the bus access control circuit in DMAC. (Refer to “Figure 13.2.2.”)

Table 13.2.1 lists the bus request generating sources.

Table 13.2.1 Bus request generating sources

Bus request

BUS REQUEST

(DRAMC)

BUS REQUEST

(Hold)

BUS REQUEST

(DMAC)

Bus request generating source

DRAM refresh request

(Generated by an underflow of the refresh timer.)

Hold request

_____

(Generated by “L”-level input to the HOLD pin.)

DMA request

(Generated by a DMA request source.)

The bus access control circuit relinquishes the right to use bus to the function with the highest priority

among functions, which issue bus requests when the BUS REQUEST signal is sampled. This is the bus

request acceptance. If any bus request is not generated at bus request sampling, the CPU gains the right

to use bus.

The bus use priority levels are fixed by hardware, and the bus status is reported by status signal outputs

ST0 and ST1. Table 13.2.2 lists the relationship between the bus use priority level, bus status, and status

signals.

Table 13.2.2 Relationship between bus use priority level, bus status, and status signals

Bus use

priority level

1 (Highest)

4 (Lowest)

Bus status

DRAM refresh

Hold

DMAC

CPU (Including the term while the CPU does not use the bus; for

example, the term when the CPU is calculating and does not use

the bus)

Status signals

ST1

ST0

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