7721 datasheet(285/577 Pages) RENESAS

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7721 Group User’s Manual

13-6

DMA CONTROLLER

13.2 Block description

Figures 13.2.1 and 13.2.2 show the DMAC block diagrams, and relevant registers are described below.

Incrementer/Decrementer

Source address register 0 (SAR0)

Destination address register 0 (DAR0)

DMA latch high-order

Address bus

Decrementer

Transfer counter register 0 (TCR0)

: Microcomputer’s internal bus

Data bus (Odd)

Data bus (Even)

Transfer counter register 1 (TCR1)

Transfer counter register 2 (TCR2)

Transfer counter register 3 (TCR3)

Source address register 1 (SAR1)

Destination address register 1 (DAR1)

Source address register 2 (SAR2)

Destination address register 2 (DAR2)

Source address register 3 (SAR3)

Destination address register 3 (DAR3)

DMA latch low-order

: DMAC’s internal bus

Fig. 13.2.1 DMAC block diagram (1)

Request

Enable

Channel 0

DMAREQ0

Software

Timer A0

TImer A1

Refresh timer

DRAM refresh

request

DRAMC

Hold request

Hold function

Array state

DMAC

DMAACK0

DMAACK1

DMAACK2

DMAACK3

Bus access

control circuit

CPU wait

request

BUS REQUEST

(DMAC)

ST0

ST1

BIU

BUS REQUEST (DRAMC)

HOLD

f16

Channel 1

Channel 2

Channel 3

BUS REQUEST (Hold)

Fig. 13.2.2 DMAC block diagram (2)

13.2 Block description

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