7721 datasheet(310/577 Pages) RENESAS

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DMA CONTROLLER

7721 Group User’s Manual

13-31

13.4 Operation

Incrementer/

Decrementer

(1) Read cycle

SARi

SARi latch

DARi

DARi latch

TCRi

TCRi latch

DMA latch

Decrementer

DMAC

Memory

(Transfer

source)

Transfer source address is specified by SARi

(Note).

Contents of TCRi are updated by decrementer

(Note)

; when value read from TCRi is “0,” transfer

of 1 data block is terminated.

Contents of SARi are updated by incrementer/

decrementer.

Data is read from memory and maintained in DMA

latch.

DMAC

V When the transfer unit is 16 bits

• When an even address is accessed with 16-bit external data bus width, data can be read or written at 1-bus

cycle. Accordingly, the incrementer/decrementer and the decrementer increment or decrement by 2, and

sequences

through

are performed once.

• When an odd address is accessed with 16-bit external data bus width or when 8 bits is used as external data

bus width, data is read or written at 2-bus cycles, and sequences

through

are repeated

twice. The incrementer/decrementer and the decrementer increment or decrement by 1 every time sequences

through

are performed once.

Note: In the single transfer mode and repeat transfer mode, only at the first transfer of the block, the values read

from SARi latch, DARi latch, and TCRi latch are used. (The results obtained by increment or decrement are

written to SARi, DARi, and TCRi. Except for the first transfer of the block, the values read from SARi, DARi,

and TCRi are used.)

(Transfer

destination)

(2) Write cycle

Memory

SARi

SARi latch

DARi

DARi latch

TCRi

TCRi latch

DMA latch

Incrementer/

Decrementer

(Transfer

source)

(Transfer

destination)

Transfer destination address is specified by DARi

(Note).

Contents of DARi are updated by incrementer/

decrementer.

Contents of DMA latch are written to memory.

(1)

Figure 13.4.2 shows a basic operation of registers for 1-unit transfer in 2-bus cycle transfer.

For register values to be specified, refer to section “13.5 Single transfer mode” through

section “13.8 Link array chain transfer mode.” It is because that these values vary according

to continuous transfer modes.

In 2-bus cycle transfer, the data read at a read cycle is maintained temporarily in the DMA

latch, and the contents of this latch are written to a memory at a write cycle.

Fig. 13.4.2 Basic operation of registers for 1-unit transfer in 2-bus cycle transfer

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