7721 datasheet(311/577 Pages) RENESAS

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7721 Group User’s Manual

13-32

DMA CONTROLLER

13.4 Operation

Read/Write cycle (Unit:

φ cycle)

Transfer

unit

16 bits

8 bits

16 bits

8 bits

External

bus width

16 bits

(including

internal

bus)

8 bits

Address directions

Fixed/Forward

Backward

Fixed/Forward/

Backward

Fixed/Forward/

Backward

Fixed/Forward/

Backward

Even

Odd

Even

Odd

Even/Odd

Data’s start

address

DRAM area

Formula

1 + i

2 + 2i

2 + i

1 + i

2 + 2i

1 + i

No Wait

2 (a)

4 (c)

3 (b)

2 (a)

4 (c)

2 (a)

With Wait

3 (d)

6 (f)

3 (d)

6 (f)

3 (d)

Address directions: Refer to section “13.4.1 (3) Address directions in 2-bus cycle transfer.”

i: A term of E = “L” in 1-bus cycle; i = 1 at “No Wait”, and i = 2 at “With Wait” or “DRAM area”.

When Ready function is used (Refer to section “3.3 Ready function.”), the number of cycles extended

by Ready must be added.

( ): Indicates the corresponding waveform in Figure 13.4.3.

Note: When a transfer destination applies to this condition, 2-bus cycle transfer cannot be performed. When

a transfer source applies to this condition and a transfer destination is in the DRAM area, 2-bus cycle

transfer cannot also be performed.

(2)

Bus operation in 2-bus cycle transfer

The time required for 1-unit transfer in 2-bus cycle transfer is given by the following formula:

Transfer time per 1-unit transfer = (Read cycle) + (Write cycle)

Since any area can be specified as a transfer source or a transfer destination, a read cycle varies

with the conditions of a transfer source, and a write cycle with that of a transfer destination.

Table 13.4.1 lists the time required for a read or write cycle per 1-unit transfer in 2-bus cycle transfer,

and Figure 13.4.3 shows the bus-cycle operation waveforms in 2-bus cycle transfer.

Table 13.4.1 Time required for a read or write cycle per 1-unit transfer in 2-bus cycle transfer

4 (e)

4 (e) (Note)

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