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7721 Group User’s Manual

13-28

DMA CONTROLLER

13.3 Control

13.3.6 DMA transfer restart after termination

(1)

Restarting the same DMA transfer as the previous one from the beginning

At normal and forced termination, the latches of SARi, DARi, and TCRi maintain their values written

before the transfer start. (Refer to “Figure 13.3.4-a.”) Therefore, DMA transfer must be restarted

according to the following procedures:

q In single or repeat transfer mode

Set the DMAi enable bit to “1.” It is not necessary to re-set the values of SARi, DARi, and TCRi

by software. (Refer to “Figure 13.3.4-b.”)

q In array chain or link array chain transfer mode

Re-set the values of SARi and TCRi.

Set the DMAi enable bit to “1.”

(2)

Restarting transfer of data subsequent to one which has been transferred just before forced

termination

When reading values at the addresses of SARi, DARi, and TCRi after forced termination, the values

of these registers (counters) can be read. These read values are the transfer source address, the

transfer destination address which were to be transferred subsequently, and the number of remaining

bytes.

When writing these read values to the addresses of SARi, DARi, and TCRi respectively, the same

values are also written to their latches. When setting the DMAi enable bit to “1” under this condition,

transfer of data subsequent to one which has been transferred just before forced termination is

restarted. (Refer to “Figure 13.3.4-c.”)

q In single transfer mode

The remaining data can be transferred by the following procedure:

Read the values at addresses of SARi, DARi and TCRi. Then, rewrite these values into these

addresses.

Set the DMAi enable bit to “1.”

q In repeat transfer, array chain transfer, and link array chain transfer modes

The remaining data of the block that was interrupted by forced termination can be transferred by

the following procedure:

Switch over the current mode to the single transfer mode.

Read the values at addresses of SARi, DARi and TCRi. Then, rewrite these values into these

addresses.

Set the DMAi enable bit to “1.” (Refer to “Figure 13.3.4-c.”)

In order to transfer the next block, switch over the current mode to the previous mode after the

above-mentioned transfer is normally terminated. Then, re-set the values of SARi, DARi, and

TCRi.

In the array chain or the link array chain transfer mode, information such as the next transfer

parameters etc. cannot be read from each latch.

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