Electronic Components Datasheet Search
  English  ▼

X  

7721 Datasheet(PDF) 304 Page - Renesas Technology Corp

Part # 7721
Description  16-BIT SINGLE-CHIP MICROCOMPUTER
PDF  577 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

7721 Datasheet(HTML) 304 Page - Renesas Technology Corp

Back Button 7721 Datasheet HTML 300Page - Renesas Technology Corp 7721 Datasheet HTML 301Page - Renesas Technology Corp 7721 Datasheet HTML 302Page - Renesas Technology Corp 7721 Datasheet HTML 303Page - Renesas Technology Corp 7721 Datasheet HTML 304Page - Renesas Technology Corp 7721 Datasheet HTML 305Page - Renesas Technology Corp 7721 Datasheet HTML 306Page - Renesas Technology Corp 7721 Datasheet HTML 307Page - Renesas Technology Corp 7721 Datasheet HTML 308Page - Renesas Technology Corp Next Button
Zoom Inzoom in Zoom Outzoom out
 304 / 577 page
background image
7721 Group User’s Manual
13-25
DMA CONTROLLER
13.3 Control
13.3.5 Termination of DMA transfer
As the methods of terminating DMA transfer, normal and forced termination are used.
(1)
Normal termination
All of the DMAi transfers terminate and DMAC stops. This method is used in the single transfer, array
chain transfer, and link array chain transfer modes. In the repeat transfer mode, however, normal
termination cannot be applied to terminating transfer; then, forced termination must be used. (Refer
to “(2) Forced termination” of this section.)
Table 13.3.4 lists the states of DMAC at normal termination.
Table 13.3.4 States of DMAC at normal termination
Item
State
DMAi interrupt request bit
DMAi request bit
DMAi enable bit
___
TC
output
Channel priority levels
1
In the burst transfer mode (edge sense): 0
In the burst transfer mode (level sense): not changed
In the cycle-steal transfer mode: not changed (Note)
0
___
Outputs “L” (when the TC pin is valid)
Rotating (when the rotating priority is selected)
Note: In the cycle-steal transfer mode, the DMAi request bit is cleared to “0” when a DMA request is
accepted. This bit is does not change at normal termination.
At normal termination, the CPU regains the right to use bus after the terminate processing (3 cycles
of
φ) via the transition of the right to use bus (1 cycle of φ). Figure 13.3.3 shows a timing example
at normal termination.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com