7721 datasheet(302/577 Pages) RENESAS

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7721 Group User’s Manual

13-23

DMA CONTROLLER

13.3 Control

13.3.4 Processing from DMA request until DMA transfer execution

DMA requests are sampled at every falling edge of

φ1; when requested, the DMAi request bit is set to “1.”

Then, the channel priority levels and bus use priority levels are determined, and BUS REQUEST (DMAC)

goes “1” if any DRAM refresh request or Hold request is not generated (Note).

BUS REQUEST (DMAC) signal is sampled while the bus request sampling signal is “1” and is accepted

(DMA request acceptance).

Figure 13.3.2 shows an example of timing from the determination of a DMA request until the DMA transfer

execution.

Refer to section “13.9 DMA transfer time” for the time from DMA request generation until the CPU’s

regaining the right to use bus via DMA transfer.

Note: In the following cases, BUS REQUEST (DMAC) does not go “1.” However, the DMAi request bit

remains set to “1.” Accordingly, after completion of each state, the channel priority levels and bus

use priority levels are determined, and BUS REQUEST (DMAC) goes “1” if any DRAM refresh

request or Hold request is not generated.

q When a DMA request is generated during a burst transfer or in an array state

(However, if a DRAM refresh request or Hold request is generated during this term, its BUS

REQUEST goes “1.”)

q When a DMA request is not accepted with a DRAM refresh request or Hold request generated

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