7721 datasheet(298/577 Pages) RENESAS

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7721 Group User’s Manual

13-19

DMA CONTROLLER

13.3 Control

The conditions for performing DMA transfer of DMAi (i = 0–3) are as follows:

• Neither a DRAM refresh request nor a Hold request is generated.

• A request of the channel with a higher priority than that of DMAi is not generated; or the request is

disabled though it has been generated.

• DMAi is enabled (DMAi enable bit = “1”).

• A DMAi request is generated (DMAi request bit = “1”).

The control method for each channel is described below.

13.3.1 DMA enabling

Each of DMA channels 0–3 has a DMAi enable bit (bits 4–7 at address 6916). Table 13.3.1 lists the

conditions for changing each DMAi enable bit.

Table 13.3.1 Conditions for changing DMAi enable bit

DMAi enable bit

Conditions for bit change

Is set to “1.”

Is cleared to “0.”

A write of “1” to the DMAi enable bit

• A write of “0” to the DMAi enable bit

• Transfer of an entire batch of data is complete (normal termination).

___

• A change of TC input level from “H” to “L” during a DMA transfer of DMAi (Note)

___

(Forced termination, when TC pin is valid.)

Note: In the burst transfer mode (level sense), however, the term from the DMA transfer start until the

transfer completion of an entire batch of data is applied. (It is also valid while the CPU has the right

to use bus.)

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