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7721 Group User’s Manual

13-20

DMA CONTROLLER

13.3 Control

13.3.2 DMA requests

(1)

DMA request sources

DMA request sources are specified by the DMA request source select bits and the edge sense/level

sense select bit. (Refer to “Figure 13.2.8.”)

Table 13.3.2 lists the conditions for generating a DMA request.

Table 13.3.2 Conditions for generating DMA request

DMA request sources

Condition for generating DMA request

Level sense

Edge sense

External source

________

DMAREQi

Software DMAi request

Timers A0–A4,

Timers B0–B2,

UART0, UART1,

A-D converter

_________

“L”-level input to the DMAREQi pin (only in the burst transfer mode)

_________

Change of the DMAREQi input pin’s level from “H” to “L”

A write of “1” to the software DMAi request bit (each of bits 0–3 at address 6916;

refer to “Figure 13.2.5.”)

When the interrupt request bit of each peripheral is set to “1” by the activity of

peripherals (If “1” is written to any of these interrupt request bits by software,

the DMAi request bit does not change. Also, whatever value within 0–7 an

interrupt priority level takes, this does not affect DMA requests.)

(2)

Change of DMAi request bit

A read of the DMAi request bits (each of bits 4–7 at address 6816) indicates whether the corresponding

channel (0–3) is generating its DMA request or not. The DMAi request bit changes synchronized with

the falling edge of

φ1. Table 13.3.3 lists the conditions for changing the DMAi request bit.

For the timing of changing the DMAi request bit, refer to “Figures 13.3.2 and 13.3.3.”

Table 13.3.3 Conditions for changing DMAi request bit

DMAi

request bit

Mode

Is set to “1.”

(Note)

Is cleared to “0.”

Generation of DMAi request

(Refer to “Table 13.3.2.”)

Generation of DMAi request

(“L”-level

input

the

_________

DMAREQi

pin)

Generation of DMAi request

(Refer to “Table 13.3.2.”)

• Normal termination

___

• Change of the TC pin’s input

level from “H ”to “L” during

___

DMA transfer (when the TC

pin is valid)

• “H”-level input to the

_________

DMAREQi pin

___

• Change of the TC pin’s input

level from “H” to “L” (when

___

the TC pin is valid)

• A write of “0” to the DMAi

request bit

• A write of “0” to the DMAi

enable bit

• Start of 1-unit transfer

___

• Change of the TC pin’s input

level from “H” to “L” during

___

DMA transfer (when the TC

pin is valid)

• A write of “0” to the DMAi

request bit

• A write of “0” to the DMAi

enable bit

Cycle-steal transfer mode

Burst transfer mode

Edge sense

Level sense

Note: While the DMAi enable bit is “0,” the DMAi request bit is not set to “1” even if a DMA request is

generated. When the DMAi enable bit is cleared to “0,” also the DMAi request bit is cleared to “0.”

However, the DMA request generated while the DMAi enable bit = “0” is maintained; and when the

DMAi enable bit is set to “1,” the DMAi request bit is also set to “1,” except for the burst transfer mode

(level sense).

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