7721 datasheet(303/577 Pages) RENESAS

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7721 Group User’s Manual

13-24

DMA CONTROLLER

13.3 Control

Fig. 13.3.2 Example of timing from determination of DMA request until DMA transfer execution

The above timing diagram applies on the following conditions:

• Single transfer mode, or Repeat transfer mode

• 2-bus cycle transfer

• No Wait

• DMAACKi valid, TC valid

• External source (DMAREQi)

• After DMAi request occurs (“L” is input to the DMAREQi pin.), the right to use bus is relinquished to DMAC

at the shortest time.

φ1

ALE

R/W

Address

Address/Data

DMAi enable bit

DMAREQi

DMAi request bit

BUS REQUEST(DMAC)

Bus request sampling

DMAACKi

ST1

ST0

DMAi interrupt

request bit

SAR

DAR

PC,PG

SAR

DAR

Data

Transition of right

to use bus

1-unit transfer

Read cycle

Write cycle

When DMAi request is

sampled at this point

Data

When Burst transfer mode (edge sense) selected

When Burst transfer mode (level sense) selected

When Cycle-steal transfer mode selected

V: Channel priority level determination and bus

use priority level determination (1.5 cycles of

φ)

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