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7721 Datasheet(PDF) 305 Page - Renesas Technology Corp |
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7721 Datasheet(HTML) 305 Page - Renesas Technology Corp |
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305 / 577 page ![]() 7721 Group User’s Manual 13-26 DMA CONTROLLER 13.3 Control The above timing diagram applies on the following conditions: • DMAACKi valid, TC valid • External source (DMAREQi) 1 ALE E R/W Address Address/Data DMAi enable bit DMAi request bit BUS REQUEST (DMAC) Bus request sampling DMAACKi TC ST1 ST0 DMAi interrupt request bit Transition of right to use bus SAR ± 1 SAR ± 1 L 0 0 When Burst transfer mode (edge sense) selected When Burst transfer mode (level sense) selected When Cycle-steal transfer mode selected Terminate processing Fig. 13.3.3 Timing example at normal termination |
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