38C3 datasheet(197/224 Pages) RENESAS

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3-52

APPENDIX

38C3 Group User’s Manual

3.5 Control registers

Fig. 3.5.26 Structure of Segment output enable register

Fig. 3.5.27 Structure of LCD mode register

Segment output enable register

b7 b6 b5 b4 b3 b2 b1 b0

Segment output enable register

(SEG: address 3816)

0: I/O ports P20–P23

1: Segment output SEG0–SEG3

Name

Functions

At reset R W

Segment output

enable bit 0

0: I/O ports P24–P27

1: Segment output SEG4–SEG7

Segment output

enable bit 1

0: I/O ports P00–P03

1: Segment output SEG8–SEG11

Segment output

enable bit 2

0: I/O ports P04–P07

1: Segment output SEG12–SEG15

Segment output

enable bit 3

0: I/O ports P10–P13

1: Segment output SEG16–SEG19

Segment output

enable bit 4

0: I/O ports P14–P17

1: Segment output SEG20–SEG23

Segment output

enable bit 5

0: Output ports P30–P33

1: Segment output SEG24–SEG27

Segment output

enable bit 6

0: Output ports P34–P37

1: Segment output SEG28–SEG31

Segment output

enable bit 7

LCD mode register

b7 b6 b5 b4 b3 b2 b1 b0

LCD mode register

(LM: address 3916)

Name

Functions

At reset R W

Duty ratio selection

bits

LCD circuit divider

division ratio selection

bits

LCDCK count source

selection bit (Note)

Bias control bit

0 0: 1 (use COM0)

0 1: 2 (use COM0, COM1)

1 0: 3 (use COM0–COM2)

1 1: 4 (use COM0–COM3)

0 0: Clock input

0 1: 2 division of clock input

1 0: 4 division of clock input

1 1: 8 division of clock input

0: 1/3 bias

1: 1/2 bias

0: f(XCIN)/32

1: f(XIN)/8192 (f(XCIN)/8192 in

low-speed mode)

LCD enable bit

Fix “0” to this bit.

0: LCD OFF

1: LCD ON

b1b0

b6b5

Note: LCDCK is a clock for a LCD timing controller.

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