38C3 datasheet(195/224 Pages) RENESAS

195 / 224 page

3-50

APPENDIX

38C3 Group User’s Manual

3.5 Control registers

Fig. 3.5.22 Structure of Timer A control register

Fig. 3.5.23 Structure of A-D control register

Timer A control register

b7 b6 b5 b4 b3 b2 b1 b0

Timer A control register

(TACON: address 3116)

Name

Functions

At reset R W

Noise filter sampling

clock selection bit

External trigger delay

time selection bits

0: f(XIN)/2

1: f(XIN)/4

0: Not used

1: INT1 interrupt used

0 0: No delay

0 1: (4/f(XIN))

µs

1 0: (8/f(XIN))

µs

1 1: (16/f(XIN))

µs

Timer A output control

bit 1 (P56)

0: Not used

1: INT2 interrupt used

Timer A output control

bit 2 (P57)

b2b1

Nothing is arranged for these bits. These are write

disabled bits. When these bits are read out, the

contents are “0”.

A-D control register

b7 b6 b5 b4 b3 b2 b1 b0

A-D control register

(ADCON: address 3216)

Name

Functions

At reset R W

Analog input pin

selection bits

b2 b1 b0

0 0 0: P60/AN0

0 0 1: P61/AN1

0 1 0: P62/AN2

0 1 1: P63/AN3

1 0 0: P64/AN4

1 0 1: P65/AN5

1 1 0: P66/AN6

1 1 1: P67/AN7

AD conversion

completion bit

0: Conversion in progress

1: Conversion completed

Nothing is arranged for these bits. These are

write disabled bits. When these bits are read

out, the contents are “0”.

Nothing is arranged for this bit. This is write

disabled bit. When this bit is read out, the

contents are “0”.

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