38C3 datasheet(198/224 Pages) RENESAS

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38C3 Group User’s Manual

3-53

APPENDIX

3.5 Control registers

Fig. 3.5.29 Structure of CPU mode register

Fig. 3.5.28 Structure of Interrupt edge selection register

Interrupt edge selection register

b7 b6 b5 b4 b3 b2 b1 b0

Interrupt edge selection register

(INTEDGE: address 3A16)

0: Falling edge active

1: Rising edge active

Name

Functions

At reset R W

INT0 interrupt edge

selection bit

0: I/O ports P24–P27

1: Segment output SEG4–SEG7

INT1 interrupt edge

selection bit

0: I/O ports P00–P03

1: Segment output SEG8–SEG11

INT2 interrupt edge

selection bit

CNTR0 active edge

switch bit

CNTR1 active edge

switch bit

Nothing is arranged for these bits. These are

write disabled bits. When these bits are read out,

the contents are “0”.

0: Falling edge active,

rising edge count

1: Rising edge active,

falling edge count

0: Falling edge active,

rising edge count

1: Rising edge active,

falling edge count

CPU mode register

b7 b6 b5 b4 b3 b2 b1 b0

CPU mode register

(CPUM, CM: address 3B16)

00 : Single-chip mode

01 :

10 :

Not available

11 :

Name

Functions

At reset R W

0 : Page 0

1 : Page 1

0: Oscillating

1: Stopped

Processor mode

bits

Stack page

selection bit

Port Xc switch bit

Nothing is arranged for this bit. When this bit is

read out, the contents is “1”. Do not write “0” to

this bit.

Main clock (XIN-

XOUT) stop bit

Main clock division

ratio selection bit

Internal system

clock selection bit

b1 b0

0: f(XIN)/2 (high-speed

mode)

1: f(XIN)/8 (middle-speed

mode)

0: XIN–XOUT selection

(middle-/high-speed

mode)

1: XCIN–XCOUT selection

(low-speed mode)

0: I/O port function

1: XCIN-XCOUT oscillation

function

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