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CDCE62005 Datasheet(PDF) 37 Page - Texas Instruments

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Part # CDCE62005
Description  Five/Ten Output Clock Generator/Jitter Cleaner With Integrated Dual VCOs
PDF  76 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

CDCE62005 Datasheet(HTML) 37 Page - Texas Instruments

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External Control Pins
CDCE62005
www.ti.com........................................................................................................................................................................................... SCAS862 – NOVEMBER 2008
Table 14. CDCE62005 Device State Definitions (continued)
Status
State
Device Behavior
Entered Via
Exited Via
Output
Output
SPI Port
PLL
Divider
Buffer
Used to shut down all hardware and
Power_Down pin is pulled LOW.
Power_Down pin is pulled HIGH.
ON
Disabled
Disabled
Disabled
Resets the device after exiting the
Power
Power Down State. Therefore, the
Down
EEPROM contents will eventually be
copied into RAM after the Power
Down State is exited.
Identical to the Power Down State
Sleep bit in device register 8 bit 7 is
Sleep bit in device register 8 bit 7 is set
ON
Disabled
Disabled
Disabled
Sleep
except the EEPROM contents are
set LOW.
HIGH.
not copied into RAM.
Sync synchronizes all output
Sync Bit in device register 8 bit 8 is
Sync Bit in device register 8 bit 8 is set
ON
Enabled
Disabled
Disabled
dividers so that they begin counting
set LOW or Sync pin is pulled LOW
HIGH or Sync pin is pulled HIGH
at the same time. Note: this
Sync
operation is performed automatically
each time a divider register is
accessed.
REF_SEL
REF_SEL provides a way to switch between the primary and secondary reference inputs (PRI_IN and SEC_IN)
via an external signal. It works in conjunction with the smart multiplexer discussed in the Input Block section.
Power_Down
The Power_Down pin places the CDCE62005 into the power down state . Additionally, the CDCE62005 loads
the contents of the EEPROM into RAM after the Power_Down pin is de-asserted; therefore, it is used to initialize
the device after power is applied. SPI_LE signal has to be HIGH in order for EEPROM to load correctly during
the rising edge of Power_Down.
SYNC
The SYNC pin (Active LOW) has a complementary register location located in Device Register 8 bit 8. When
enabled, Sync synchronizes all output dividers so that they begin counting simultaneously. Further, SYNC
disables all outputs when in the active. State.
Copyright © 2008, Texas Instruments Incorporated
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