CDCE62005 datasheet(7/76 Pages) TI

7 / 76 page

Input Block

/1:/2:HiZ

ReferenceDivider

/1-/8

PRI_IN

SEC_IN

XTAL/

AUX_IN

1500MHz

LVPECL:1500MHz

LVDS:800MHz

LVCMOS:250MHz

1500MHz

Crystal:2MHz-40MHz

SingleEnded:2MHz-75MHz

Smart

MUX1

Smart

MUX2

SmartMUX

Control

REF_SEL

CDCE62005

www.ti.com........................................................................................................................................................................................... SCAS862 – NOVEMBER 2008

The Input Block includes a pair of Universal Input Buffers and an Auxiliary Input. The Input Block buffers the

incoming signals and facilitates signal routing to the Internal Clock Distribution bus and the Synthesizer Block via

the smart multiplexer (called the Smart MUX). The Internal Clock Distribution Bus connects to all output blocks

discussed in the next section. Therefore, a clock signal present on the Internal Clock Distribution bus can appear

on any or all of the device outputs. The CDCE62005 routes the PRI_IN and SEC_IN inputs directly to the Internal

Clock Distribution Bus. Additionally, it can divide these signals via the dividers present on the inputs and output

of the first stage of the Smart MUX.

Figure 5. CDCE62005 Input Block

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CDCE62005 Datasheet(PDF) 7 Page - Texas Instruments

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