CDCE62005 datasheet(42/76 Pages) TI

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8pF

CDCE62005

SCAS862 – NOVEMBER 2008........................................................................................................................................................................................... www.ti.com

Table 18. CDCE62005 Pre-Divider Settings (continued)

Primary Pre-Divider

Secondary Pre-Divider

Bit Name

→

DIV2PRIY

DIV2PRIX

Bit Name

→

DIV2SECY

DIV2SECX

→

0.1

0.0

Divide Ratio

→

1.1

1.0

Divide Ratio

Reserved

The CDCE62005 provides a Reference Divider that divides the clock exiting the first multiplexer stage; thus

dividing the primary (PRI_IN) or the secondary input (SEC_IN).

Table 19. CDCE62005 Reference Divider Settings

Reference Divider

Bit Name

→

REFDIV2

REFDIV1

REFDIV0

Divide Ratio

→

3.0

2.1

2.0

Auxiliary Input Port

The auxiliary input on the CDCE62005 is designed to connect to an AT-Cut Crystal with a total load

capacitance(CL) of 0 to 10pF. One side of the crystal connects to Ground while the other side connects to the

Auxiliary input of the device. The circuit works optimally between 20 to 40MHz but it can accept crystals from 2 to

42MHz.

Since the Auxiliary input operates between 0 and 2 V with a crystal, it can accept single-ended signals (e.g.

LVCMOS). Electrically, it is equivalent to an LVCMOS input buffer with 10pf of input capacitance.

Figure 27. CDCE62005 Auxiliary Input Port

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