CDCE62005 datasheet(70/76 Pages) TI

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DataConverterJitterRequirements

100

110

120

130

140

100

1000

10000

50fs

100fs

350fs

1ps

SERDES

CleanedClock

Data

CDCE 62005

RecoveredClock

ASICClock

ASIC

CDCE62005

SCAS862 – NOVEMBER 2008........................................................................................................................................................................................... www.ti.com

Figure 44. Data Converter Jitter Requirements

CDCE62005 SERDES Startup Mode

A common scenario involves a host communicating to a satellite system via a high-speed wired communications

link. Typical communications media might be a cable, backplane, or fiber. The reference clock for the satellite

system is embedded in the high speed link. This reference clock must be recovered by the SERDES, however,

the recovered clock contains unacceptable levels of jitter due to a degradation of SNR associated with

transmission over the media. At system startup, the satellite system must self-configure prior to the recovery and

cleanup of the reference clock provided by the host. Furthermore, upon loss of the communication link with the

host, the satellite system must continue to operate albeit with limited functionality. Figure 45 shows a block

diagram of an optical based system with such a mechanism that takes advantage of the features of the

CDCE62005:

Figure 45. CDCE62005 SERDES Startup Overview

The functionality provided by the Smart Multiplexer provides a straightforward implementation of a SERDES

clock link. The Auxiliary Input provides a startup clock because it connects to a crystal. The on-chip EEPROM

determines the default configuration at power-up; therefore, the CDCE62005 requires no host communication to

begin cleaning the recovered clock once it is available. The CDCE62005 immediately begins clocking the

satellite components including the SERDES using the crystal as a clock source and a frequency reference. After

the SERDES recovers the clock, the CDCE62005 removes the jitter via the on-chip synthesizer/loop filter. The

recovered clock from the communications link becomes the frequency reference for the satellite system after the

smart multiplexer automatically switches over to it. The CDCE62005 applies the cleaned clock to the recovered

clock input on the SERDES; thereby establishing a reliable communications link between host and satellite

systems.

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