CDCE62005 datasheet(41/76 Pages) TI

41 / 76 page

PRI _ REF

SEC _ REF

Internal

ReferenceClock

PrimaryClock

SecondaryClock

PrimaryClock

/1:/2:HiZ

ReferenceDivider

/1 - /8

PRI_IN

SEC _IN

XTAL /

AUX _IN

Smart

MUX1

Smart

MUX2

SmartMUX

Control

REF_SEL

SmartMultiplexer

AuxiliaryInput

UniversalInputBuffers

CDCE62005

www.ti.com........................................................................................................................................................................................... SCAS862 – NOVEMBER 2008

Smart Multiplexer Auto Mode

Smart Multiplexer Auto Mode switches automatically between clock inputs based on a prioritization scheme

shown in Table 17. If using the Smart Multiplexer Auto Mode, the frequencies of the clock inputs may differ by up

to 20%. The phase relationship between clock inputs has no restriction. The smart multiplexer includes signal

conditioning that provides glitch suppression(1).

Upon the detection of a loss of signal on the highest priority clock, the smart multiplex switches its output to the

next highest priority clock on the first incoming rising edge of the next highest priority clock. During this switching

operation, the output of the smart multiplexer is low. Upon restoration of the higher priority clock, the smart

multiplexer waits until it detects four complete cycles from the higher priority clock prior to switching the output of

the smart multiplexer back to the higher priority clock. During this switching operation, the output of the smart

multiplexer remains high until the next falling edge as shown in Figure 25.

Figure 25. CDCE62005 Smart Multiplexer Timing Diagram

Smart Multiplexer Dividers

Figure 26. CDCE62005 Smart Multiplexer

The CDCE62005 Smart Multiplexer Block provides the ability to divide the primary and secondary UIB or to

disconnect a UIB from the first state of the smart multiplexer altogether.

Table 18. CDCE62005 Pre-Divider Settings

Primary Pre-Divider

Secondary Pre-Divider

Bit Name

→

DIV2PRIY

DIV2PRIX

Bit Name

→

DIV2SECY

DIV2SECX

→

0.1

0.0

Divide Ratio

→

1.1

1.0

Divide Ratio

Hi-Z

(1)

This implementation does not include a phase build-out mechanism.

Submit Documentation Feedback

Product Folder Link(s) :CDCE62005

CDCE62005 Datasheet(PDF) 41 Page - Texas Instruments

CDCE62005 Datasheet(HTML) 41 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76

Datasheet Download

Link URL