CDCE62005 datasheet(65/76 Pages) TI

65 / 76 page

DEVICE POWER CALCULATION AND THERMAL MANAGEMENT

DieTemperaturevsTotalDevicePower

100

125

Power(W)

JEDEC0LFM25C

JEDEC100LFM25C

RL 0LFM25C

RL 100LFM25C

JEDEC0LFM85C

JEDEC100LFM85C

RL 0LFM85C

RL 100LFM85C

JEDEC0LFM25C

JEDEC100LFM25C

RL 0LFM25C

JDEC0LFM85C

JEDEC100LFM85C

RL 0LFM85C

RL 100LFM85C

RL 100LFM25C

CDCE62005

www.ti.com........................................................................................................................................................................................... SCAS862 – NOVEMBER 2008

The CDCE62005 is a high performance device, therefore careful attention must be paid to device configuration

and printed circuit board layout with respect to power consumption. Table 44 provides the power consumption for

the individual blocks within the CDCE62005. To estimate total power consumption, calculate the sum of the

products of the number of blocks used and the power dissipated of each corresponding block.

Table 44. CDCE62005 Power Consumption

Internal Block (Power at 3.3V)

Power Dissipated per Block

Number of Blocks per Device

Input Circuit

18 mW

PLL and VCO Core

746 mW

Output Divider

185 mW

Output Buffer ( LVPECL)

116 mW

Output Buffer (LVDS)

76 mW

Output Buffer (LVCMOS)

86 mW

This power estimate determines the degree of thermal management required for a specific design. Employing the

thermally enhanced printed circuit board layout shown in Figure 39 insures that the thermal performance curves

shown in Figure 38 apply. Observing good thermal layout practices enables the thermal pad on the backside of

the QFN-48 package to provide a good thermal path between the die contained within the package and the

ambient air. This thermal pad also serves as the ground connection the device; therefore, a low inductance

connection to the ground plane is essential.

Figure 39 shows a layout optimized for good thermal performance and a good power supply connection as well.

The 7×7 filled via patter facilitates both considerations. Finally, the recommended layout achieves

JA =

27.3°C/W in still air and 20.3°C/W in an environment with 100 LFM airflow if implemented on a JEDEC compliant

thermal test board..

Figure 38. CDCE62005 Die Temperature vs Device Power

Submit Documentation Feedback

Product Folder Link(s) :CDCE62005

CDCE62005 Datasheet(PDF) 65 Page - Texas Instruments

CDCE62005 Datasheet(HTML) 65 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76

Datasheet Download

Link URL